Code: digcElectronics & Comm. Eng.3rd Semester1 Examination Papers

Digital Circuits

Official Bihar Engineering University examination question papers, marks distribution, and questions transcript. Available exam sessions: 2023.

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Official Exam Paper TranscriptEnd Semester Examination - 2023
Bihar Engineering University, Patna
End Semester Examination - 2023

Digital Circuits

Time: 03 HoursCode: 104403Full Marks: 70

Instructions:

  1. The marks are indicated in the right-hand margin.
  2. There are NINE questions in this paper.
  3. Attempt FIVE questions in all.
  4. Question No. 1 is compulsory.
Q.1 Write the short answer of the following (Any seven question only):[14]
  1. Find the hexadecimal equivalent of the decimal number 256.

  2. What is meant by weighted and non-weighted coding?

  3. State Demorgan's theorem.

  4. What do you mean by carry propagation delay?

  5. What do you mean by Encoder?

  6. What are the primary disadvantages of an asynchronous counter?

  7. What are races and cycles?

  8. Why is MUX called as data selector?

  9. When can RTL be used to represent digital system?

  10. Draw the DTL based NAND gate.

Q.2 Solve both questions :[10+4=14]
  1. Describe the procedure to design of asynchronous sequential circuit in detail with an example.

  2. What are the disadvantages of asynchronous sequential circuit?

Q.3 Solve both questions :[10+4=14]
  1. Explain the characteristics and about TTL parameters. Discuss implementation of the following digital logic families : (a) CMOS (b) TTL

  2. Discuss about TTL parameters.

Q.4 Solve both questions :[7+7=14]
  1. Explain the realization of JK flipflop from T flipflop.

  2. Design a 4-bit BCD ripple counters.

Q.5 Solve this question :[14]
  1. What is meant by magnitude comparator? Discuss in detail about two bit magnitude comparator.

  2. Design a full adder using NOR gates.

Q.6 Solve both questions :[7+7=14]
  1. Explain briefly about SOP and POS forms with example.

  2. Plot the logical expression ABCD+AoverlineBoverlineCoverlineD+AoverlineBC+AB on a 4 variable K-map. Obtain the simplified expression from the map.

Q.7 Solve both questions :[7+7=14]
  1. How does don't care condition in K-map help for circuit simplification?

  2. Write the POS form of the SOP expression f(x,y,z)=overlineXYZ+XYoverlineZ+XoverlineYZ.

Q.8 Solve both questions :[7+7=14]
  1. Implement the following function using suitable multiplexer. F(a,b,c)=Σm(3,4,5,7).

  2. Implement JK flipflop using SR flipflop.

Q.9 Write Short notes on any two of the following:[14]
  1. Analog to Digital Converter

  2. Multivibrator

  3. Monostable and Astable timer

Related Official Syllabus

Check the complete official BEU syllabus for Electronics & Comm. Eng. 3rd Semester to view credit allocations, recommended textbooks, and topics.

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